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general description the ds1861 is a laser-driver control ic designed to reduce the production cost of fiber optics circuits by eliminating multiple temperature tests. it works with nearly all laser-driver ics to provide automatic power control (apc) and automatic extinction ratio control (aerc), which improves the performance of the system over temperature and aging. it also has built-in monitor- ing capability to provide early fault detection, which can be configured to latch the ic into a shutdown condition. settings programmed into the ds1861 are stored in password-protected eeprom memory, which write- protects calibration data. programming is accom- plished through an i 2 c-compatible interface, which can also be used to read diagnostic information. applications optical transceivers optical transponders features ? automatic power control (apc) ? automatic extinction ratio control (aerc) across temperature and laser aging ? works in ac-coupled laser systems ? configurable latched automatic shutdown with tx-fault and tx-disable ? programmable fast alarm conditions ? i 2 c-compatible serial interface allows up to eight devices on the same serial bus ? operates over wide supply-voltage range ? nonvolatile memory for device settings ? small, 14-pin tssop package ? -40? to +95? operating temperature range ds1861 full laser control with fault management ______________________________________________ maxim integrated products 1 tx-d gnd v cc n.c. a2 a1 tx-f sda scl 4.7k ? 4.7k ? v cc 4.7k ? n.c. ds1861 a0 30k ? v cc v cc biasset bias i biasset i modset mod out bias laser driver modset bmd i bmd 1nf max3736 t ypical operating circuit rev 0; 5/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configuration appears at end of data sheet . ordering information purchase of i 2 c components from maxim integrated products, inc., or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. part temp range pin-package ds1861e -40? to +95? 14 tssop (173 mils) ds1861e+ -40? to +95? 14 tssop (173 mils) + denotes lead free.
ds1861 full laser control with fault management 2 _____________________________________________________________________ absolute maximum ratings recommended operating conditions (v cc = +2.85v to 5.5v, t a = -40? to +95?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc , sda, and scl pins relative to ground.....................................-0.5v to +6.0v voltage range on a 0 , a 1 , a 2 , tx-fault, tx-disable, biasset, modset, and bmd relative to ground.................-0.5v to (v cc + 0.5v), not to exceed +6.0v operating temperature range ...........................-40? to +95? eeprom programming temperature range .........0? to +70? storage temperature range .............................-55? to +125? soldering temperature .......................................see ipc/jedec j-std-020 specification parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.85 5.50 v input logic 1 (sda, scl, a 2 , a 1 , a 0 ) v ih1 0.7 x v cc v cc + 0.3 v input logic 0 (sda, scl, a 2 , a 1 , a 0 ) v il1 -0.3 +0.3 x v cc v input logic 1 (tx-d) v ih2 1.5 v input logic 0 (tx-d) v il2 0.9 v voltage at biasset and modset 0.6 3.0 v i th /i apc ratio (note 2) 7:1 dc electrical characteristics (v cc = +2.85v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units supply current i cc (note 3) 5 7 ma input leakage i li -1 +1 ? output leakage (tx-f, sda) i lo high impedance -1 +1 ? v ol1 3ma sink current 0 0.4 low-level output voltage (tx-f, sda) v ol2 6ma sink current 0 0.6 v i/o capacitance c i/o 10 pf input current each i/o pin 0.4 < v i/o < 0.9 x v dd -10 +10 ?
ds1861 full laser control with fault management _____________________________________________________________________ 3 analog output characteristics (v cc = +2.85v to 5.5v; t a = -40? to +95?.) parameter symbol conditions min typ max units biasset current range i biasset 0.01 1.50 ma biasset shutdown current 10 100 na modset current range i modset 0.01 1.20 ma modset shutdown current 10 100 na apc calibration accuracy ( error in setting i bmd ) (note 4) 3 % apc temp drift (% drift in i bmd ) (note 5) ? ? % 40a < i m od s e t < 100? at + 25 o c ( n ote 6) 1 4 100? < i m od s e t < 400? at + 25 o c ( n ote 6) 1 3 n temp drift i m od s e t > 400? at + 25 o c ( n ote 6) 1 ?.75 % extinction ratio calibration accuracy at 10db extinction ratio 0.22 db loop transient settling error i biasset and i modset after 300ms 3 % extinction ratio update frequency f eru 525hz peak bmd disturbance current i dist percent increase above i bmd 3.33 3.60 % analog input characteristics (v cc = +2.85v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units bmd current?ource or sink (? i set (note 7) 0.05 1.50 ma bmd voltage v bmd i bmd = 0.5x to 2x i set 1.0 1.24 1.5 v gain = 16 175 265 350 gain = 8 350 530 700 gain = 4 700 1060 1400 gain = 2 1400 2120 2800 bmd input resistance r bmd i bmd = i set ?0% (i set ) gain = 1 2800 4240 5600 ? reference voltage v ref 1.24 v
ds1861 full laser control with fault management 4 _____________________________________________________________________ fast alarms and v cc monitor characteristics (v cc = +2.85v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units high bias alarm lsb 255 settings (includes off) 8.2 ? high bias alarm threshold accuracy high bias settings > 100? 10 % ltxp_thres (bin) xxxxx000 ltxp alarm off xxxxx001 do not use xxxxx010 0.81 xxxxx011 0.76 xxxxx100 0.54 xxxxx101 0.41 xxxxx110 0.28 ltxp alarm threshold multiplier (i set multiplier shown, note 8) xxxxx111 0.14 ma/ma htxp_thres (bin) xxxxx000 htxp alarm off xxxxx001 do not use xxxxx010 1.30 xxxxx011 1.43 xxxxx100 1.56 xxxxx101 1.69 xxxxx110 1.82 htxp alarm threshold multiplier (i set multiplier shown, note 8) xxxxx111 1.95 ma/ma v cc power good v poa 2.15 2.70 v vcc fault deassert delay t poar 360 700 ? digital power-on reset voltage v pod 1.0 2.2 v i 2 c ac electrical characteristics (v cc = +2.85v to 5.5v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) .) (figure 14) parameter symbol conditions min typ max units scl clock frequency f scl (note 9) 0 400 khz bus free time between stop and start conditions t buf 1.3 ? hold time (repeated) start condition t hd:sta 0.6 ? low period of scl t low 1.3 ? high period of scl t high 0.6 ? data hold time t hd:dat 0 0.9 ?
ds1861 full laser control with fault management _____________________________________________________________________ 5 i 2 c ac electrical characteristics (continued) (v cc = +2.85v to 5.5v, t a = -40? to +95?, timing referenced to v il(max) and v ih(min) .) (figure 14) parameter symbol conditions min typ max units data setup time t su:dat 100 ns start setup time t su:sta 0.6 ? sda and scl rise time t r (note 10) 20 + 0.1c b 300 ns sda and scl fall time t f (note 10) 20 + 0.1c b 300 ns stop setup time t su:sto 0.6 ? sda and scl capacitive loading c b (note 10) 400 pf eeprom write time t w (note 11) 10 20 ms power-supply ac electrical characteristics (v cc = +2.85v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units supply slew rate dv/dt vcc v cc = 0 to 5.5 (note 12) 30 v/ms shutdown and fault ac electrical characteristics (v cc = +2.85v to 5.5v, t a = -40? to +95?.) parameter symbol conditions min typ max units biasset and modset disable (10% of active level) t off from rising edge of tx-d 5 ? apc recovery from normal disable (to i bmd 90% level) t on:b from falling edge of tx-d (note 13) 0.8 ms modulation recovery from normal disable (to i moddriver 90% level) t on:m from falling edge of tx-d (note 14) 0.2 ms apc recovery after power-up or shutdown (to i bmd 90% level) t init:b (note 13) 0.8 ms modulation recovery after power-up or shutdown (to i moddriver 90% level) t init:m 100 ms fault reset time (to tx-fault = 0) t init:f 100 150 ms shutdown time (to 10% i biasset , 10% i modset , tx-f high) t fault i bmd > htxp threshold, or i bias hbias threshold, or i bmd < ltxp threshold 50 ? minimum reset pulse width t reset 1s
ds1861 full laser control with fault management 6 _____________________________________________________________________ nonvolatile memory characteristics (v cc = +2.85v to 5.5v, t a = 0? to +70?.) parameter symbol conditions min typ max units writes +70? (note 15) 50,000 note 1: all voltages are referenced to ground. currents into the ic are positive, out of the ic negative. note 2: the threshold current (i th ) to light producing current (i apc ) ratio should remain below 7:1. this limits overshoot to under 10% and ensures the data sheet accuracies are met. note 3: max i cc is dependent on scl clock rates. note 4: calibration accuracy refers to the accuracy achieved at the end of calibration. note 5: this specification refers to the error contribution due to this chip, and does not include the error due to the drift of the mo n- itor-diode responsivity with temperature. note 6: the n temperature drift specification includes error caused by changes in modulation current due to system temperature variation. after the part is calibrated at +25?, this spec allows for modulation current changes of up to +65% with increas- ing temperature and -25% with decreasing temperature. larger modulation current variations would have increased drift, but this range accommodates a reasonable change (up to 2x across temperature) in laser diode slope efficiency. calibration is assumed to take place at +25? for the purposes of this spec. this does not imply that the system must be calibrated at +25?. note 7: within the apc calibration accuracy. note 8: values in the table are multiplied times the i bmd set point (set by apc register) to determine the threshold limits. note 9: i 2 c interface timing shown is for fast-mode (400khz) operation. this device is also backward compatible with i 2 c stan- dard-mode timing. note 10: c b ?otal capacitance of one bus line in pf. note 11: eeprom write begins after a stop condition occurs. note 12: if the supply ramps up at slew rates within the specification, the device will be functional after v cc exceeds v poa and the power-up time (t poar ) elapses. note 13: on power-up and when tx-d is deasserted, ibiasset ramps up from zero current to its final value with 10% apc over- shoot during the transient. note 14: modulation is applied at the level it was at before disable. if the time from disable is so long that the laser has cooled down, then meeting er accuracy is contingent upon completion of the first er update. the modload enable bit and modload register can be used to load a predetermined i modset value if desired. see the detailed register descriptions section for more information. note 15: this parameter is guaranteed by design.
ds1861 full laser control with fault management _____________________________________________________________________ 7 v cc > v poa t poar t init:f t init:b t init:m tx-d tx-f i biasset i modset timing diagrams figure 1. power-up timing with tx-d not asserted (including hotplug) v cc > v poa tx-d tx-f i biasset i modset t init:b t init:m t init:f figure 2. power-up timing with tx-d asserted
ds1861 full laser control with fault management 8 _____________________________________________________________________ tx-d *tx-f will assert if the htxp alarm is triggered while the bias currents are disabled. the ltxp alarm is masked while tx-d is asserted. first control loop adjustment of i modset after tx-d is deasserted tx-f * i biasset i modset t off t off t on:m t init:m t on:b timing diagrams (continued) figure 3. tx-d timing during normal operation occurence of fault tx-d tx-f i biasset i modset t f ault t f ault t f ault figure 4. detection of transmitter safety fault condition
ds1861 full laser control with fault management _____________________________________________________________________ 9 t reset t init:b t init:f t init:m occurence of fault tx-d tx-f i biasset i modset timing diagrams (continued) figure 5. successful recovery from transmitter safety fault condition t reset t init:m occurence of fault tx-d tx-f i biasset tx-f remains high during an unsuccessful recovery due to the internal timer. i biasset and i modset may have to bias the part to recreate the shutdown condition. i modset figure 6. unsuccessful recovery from transmitter safety fault condition
ds1861 full laser control with fault management 10 ____________________________________________________________________ t ypical operating characteristics (v cc = +5.0v, t a = +25?, unless otherwise noted.) supply current vs. supply voltage ds1861 toc01 supply voltage (v) supply current (ma) 5.35 4.85 4.35 3.85 3.35 5.4 5.9 6.4 6.9 4.9 2.85 dpol = 0, t a = +85 c dpol = 0, t a = +25 c dpol = 0, t a = -40 c dpol = 1, t a = +25 c dpol = 1, t a = +85 c dpol = 1, t a = -40 c gain = 4, apc = 16, ext. loop gain = 1 supply current vs. temperature ds1861 toc02 temperature ( c) supply current (ma) 60 35 10 -15 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 7.0 6.0 -40 85 dpol = 0 dpol = 1 v cc = 5.0v, apc = 4, gain = 16 i bmd drift vs. supply voltage ds1861 toc03 supply voltage (v) i bmd drift (%) 5.35 4.85 4.35 3.85 3.35 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.85 t a = 25 c, apc = 16, gain = 4 dpol = 1 dpol = 0 i bmd drift vs. temperature ds1861 toc04 temperature ( c) i bmd drift (%) 60 35 10 -15 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.8 -40 85 dpol = 1 dpol = 0 v cc = 5.0v, apc = 16, gain = 4 tx-f output current vs. output voltage ds1861 toc05 output voltage output current (ma) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 5 10 15 20 25 30 0 01.0 v cc = 2.85v n drift vs. temperature ds1861 toc06 temperature ( c) n drift (%) 85 60 35 10 -15 -2 -1 0 1 2 3 -3 -40 i modset = 100 a i modset = 400 a i modset = 40 a v cc = 2.85v, dpol = 0, n = 30
ds1861 full laser control with fault management ____________________________________________________________________ 11 pin description 11 ___________________________________________________________________________________________________ pin name function 1 sda serial data input/output. i 2 c bidirectional data pin, which requires a pullup resistor to realize high logic levels. 2 scl serial clock input. i 2 c clock input. 3 tx-f transmit fault output. open-collector output that indicates an alarm condition has occurred. a pullup resistor is required on this pin to realize high logic levels. 4 tx-d transmit disable input 5, 8 n.c. no connection 6 bmd photodiode current input 7 gnd ground 9 biasset bias current output 10 a 0 11 a 1 12 a 2 i 2 c address inputs. these inputs determine the slave address of the device. the slave address in binary is 1010a 2 a 1 a 0 . 13 modset modulation current ouput 14 v cc power supply
ds1861 full laser control with fault management 12 ____________________________________________________________________ functional diagram with settings p assword protection disturbance current user eeprom (8 bytes) i 2 c-compatible interface automatic power control quick trip f ault monitor automatic extinction ratio control nonvolatile nonvolatile nonvolatile current sink/source i set v ref i bmd r bmd i bmd i bmd i b i b i dist biasset modset bmd current sense ds1861 v cc v cc sda scl a 2 a 1 a 0 tx-d tx-f gnd v cc detailed description automatic power control the ds1861 apc is accomplished by adjusting the bias current (i bias ) until the feedback current (i bmd ) from a photodiode matches the value determined by the apc register. the relationship between the apc register and i bmd is given by: i set = 1.525? gain (apc<4:0> + 32) where apc<4:0> is the numerical value determined by the five least significant bits of the apc register, and the gain value is determined by the upper three bits of the apc register, as shown in the truth table below. see figure 7 for a graph of the bmd current-set point vs. the apc register value. the bmd pin appears to the photodiode as a voltage source (v ref ) with an output resistance equal to r bmd in parallel with a current source (i set ) equal to the i bmd setpoint. when the control loop is at its steady state value, the voltage at the bmd pin (v bmd ) is equal to v ref , and the bmd current will all be sourced by i set . when an imbalance causes the feedback current to differ from the set current, the difference in the currents causes the ds1861 to adjust the biasset and the modset cur- rents to new settings so the input current matches the set current. during transient periods, the difference in the i set and i bmd currents causes a small current to pass through r bmd . this causes a slight increase or decrease in the v bmd voltage. the current source can sink and source current, which must be configured using the dpol bit in the control byte for proper operation. this allows the photodiode to be referenced to either v cc or gnd. see the memory map and detailed register descriptions sections for more detail. apc<7:5> gain 000 1 001 2 010 4 011 8 1xx 16
reading the biasset and modset registers the i biasset and i modset currents are generated by embedded 18-bit and 12-bit dacs, respectively, and their output currents can be read when the ds1861 has been halted using the halt bit, and the password has been entered. see the detailed register descriptions section for information on calculating the output current from the register? value. automatic extinction ratio control the ds1861 injects a small disturbance current to mea- sure the gain (light/ma) of the laser driver and laser diode pairing. this control methodology makes the extinction ratio insensitive to changes in the photodi- ode? responsivity due to temperature and aging effects, as long as the ratio of the laser driver? bias current gain (a d ) and modulation current gain (a m ) remains constant (figure 8). the disturbance current is automatically scaled as the bmd current-set point is adjusted, so the peak distur- bance current always increases i bmd by approximately 3.3%. see figure 9 for details. to understand how the modset and biasset currents control the extinction ratio, the extinction ratio equation (extinction ratio = p1/p0) must first be expressed in terms of the modulation power (p mod ) and average power (p avg ). figure 10 shows the current and power levels that correspond to the optical logic 1 (p1) and logic 0 (p0) levels. extinction ratio p p pp pp avg mod avg mod == + ? 1 0 1 2 1 2 ds1861 full laser control with fault management ____________________________________________________________________ 13 0 0.375 0.750 1.500 1.125 0 128 64 192 255 ds1861 fig07 apc register setting (decimal) i set (ma) figure 7. bmd current setpoint vs. apc register setting ds1861 biasset i biasset biasref modref bias mod i modset photo- diode laser driver laser diode light *i d = i bias i mod 1 2 a d ac-coupling circuitry i bias i d * i mod a m i bmd modset bmd figure 8. aerc block diagram
ds1861 once the extinction ratio is expressed as a function of the average power and the modulation power, the equation can then be written in terms of the modulation and average power currents. the modulation current (i mod ) is defined as the difference between the i 1 and i 0 currents (i mod = i 1 - i 0 ). the average power current (i apc ) is the arithmetic mean of the i 1 and i 0 currents referenced to the threshold current (i apc = 1 / 2 i 1 + 1 / 2 i 0 - i th ). after defining these currents, the equation can now be rewritten as the following equations. the apc loop is already controlling i apc to keep the average power at a constant value, so the ds1861 out- puts i modset so that i mod /i apc remains constant to control the extinction ratio. the ds1861 determines the i mod /i apc ratio according to the following formula, where n is a variable gain that can be used to adjust the extinction ratio. substituting into the previous extinction ratio equation yields the extinction ratio as a function of n. extinction ratio na a na a n a a n a a m d m d m d m d = + = + ?? 1 1 230 1 1 230 60 60 i i n x a a mod apc m d = 30 extinction ratio ii ii i i i i apc mod apc mod mod apc mod apc = + = + ?? 1 2 1 2 1 1 2 1 1 2 full laser control with fault management 14 ____________________________________________________________________ figure 9. bmd disturbance current figure 10. laser diode bias current definitions ds1861 fig09 time bmd current i dist 1 f eru ds1861 fig10 current (ma) p0 i mod 2 i mod 2 i 1 i 0 p1 average power p mod i mod i apc i th
figure 11 shows the extinction ratios (expressed in decibels) as a function of n for several a m /a d ratios. note the actual extinction ratio value is determined by the ratio a m /a d in addition to n. if the a m /a d ratio varies due to voltage, temperature, or aging effects, it becomes an additional error source when determining the overall extinction ratio variance. the ds1861 is meant to be used with a monolithic laser driver, where a m and a d are generated on the same chip, so changes in the ratio of a m to a d are minimal. the n value itself is determined by the extinction ratio register. there are two components of the er register used to calculate n. the range select bit (rsel), which selects the high (rsel = 1) or low (rsel = 0) range of n, is the msb of the register. the lower seven bits of the register (er<6:0>) determine the value of n within the selected range. the value of n is given by: the er<6:0> value should be programmed to values between 28 and 104 (decimal), regardless if the high or low range is selected, to ensure that the n value remains accurate and constant as intended. these lim- its allow the n values of the high and low range to over- lap to ensure that all n values can be attained, but prevents potential errors that can be caused by using the extremes of each rsel range. figure 12 shows the n values as a function of the er register setting. the convergence algorithm and overshoot control the ds1861 uses a tiered slew-rate control system that adjusts the dac update rate and the number of lsbs it increases/decreases per update cycle when the control loop is seeking to converge to its steady state value. for the apc loop, it makes its decision on the required con- vergence rate based on the percent error between the present bmd current and the bmd current-set point. the modulation current slew rate is adjusted based solely on the difference between its present code and the code-set point that is determined by the aerc cir- cuitry. both update rates are designed to prevent any overshoot during large set-point changes in excess of 10%, which assumes (see the following) the ratio of the laser diode? threshold current (i th ) to the average power current (i apc ) is below 7:1. most systems do not exhibit any overshoot when using the ds1861. : : n er when rsel er when rsel = <>+ = <>+ = ? ? ? ? ? 60 32 2 0 60 32 1 ds1861 full laser control with fault management ____________________________________________________________________ 15 extinction ratio (am/ad = 1.2) vs. er setting ds1861 fig11a er setting (decimal) extinction ratio (db) 96 80 64 48 32 5 10 15 20 25 0 16 112 rsel = 0 extinction ratio (am/ad = 0.8) vs. er setting ds1861 fig11b er setting (decimal) extinction ratio (db) 96 80 64 48 32 5 10 15 20 25 0 16 112 extinction ratio (am/ad = 0.4) vs. er setting ds1861 fig11c er setting (decimal) extinction ratio (db) 96 80 64 48 32 5 10 15 20 25 0 16 112 rsel = 0 rsel = 0 rsel = 1 rsel = 1 figure 11. typical extinction ratios vs. n codes
ds1861 the average power current is defined as the difference between the current required to reach the average power output and the threshold current of the laser diode. the average power output is defined as the mean of the power used to transmit a high logic level (p1) and the power used to transmit a low power level (p0). figure 10 graphically shows the threshold and average power currents as they relate to the light out- put of a laser diode. fault monitors and shutdown the ds1861 has a v cc monitor plus three programma- ble quick-trip (qt) fault monitors (figure 13) that can trigger the tx-f output. the qts monitor for high trans- mit power (htxp), low transmit power (ltxp), and for high bias current (hbias). all the qts feature program- mable trip levels, an alarm disable, and a shutdown enable to determine if the enabled qt alarm shuts off the i biasset and i modset outputs. v cc is monitored against two internal voltage levels to ensure that v cc is at an adequate level for the part to full laser control with fault management 16 ____________________________________________________________________ figure 12. setting n using the er register ds1861 fig12 er register setting (decimal) n 104 105 27 28 16 32 48 64 80 96 112 128 144 0 127 invalid invalid invalid er settings shaded high range (rsel = 1) low range (rsel = 0) figure 13. quick trip logic diagram biasset rst out in in s r d q q f ault reset timer (130ms) out quickstart modload enable tx-f shutdown flag control logic modset s r d q q s hbias shutdown l txp alarm l txp enable htxp alarm htxp enable hbias alarm hbias enable tx-d note: poa is high when v cc < v poa . soft tx-d poa htxp shutdown lt xp shutdown r d q q
communicate over the i 2 c bus and for the analog cir- cuitry to function properly. the first monitoring level, the power-on digital voltage (v pod ), inhibits the part? i 2 c functionality when v cc is below v pod . the second monitoring level is the power-on analog voltage (v poa ). the ds1861 disables i biasset and i modset and asserts the tx-f output whenever v cc is below v poa . both v cc monitors are nonmaskable, so there is no way to force the chip to function when v cc is not at an ade- quate level to assure the ds1861 operates properly. the high and low transmit power quick-trip thresholds are each programmed by 3 bits that select one of seven different levels as a function of the expected i bmd current. each qt monitor can be disabled by pro- gramming all three bits to zero. disabling a qt by pro- gramming its control bits to zero prevents the qt alarm flags from ever being set, which consequently prevents that monitor from asserting the tx-f output, latching the device into a shutdown condition, or setting the alarm bits in the status register. the htxp and ltxp enable bits can be used to prevent the transmit power level qts from causing shutdown while allowing the tx-f output to be set to flag the system of a transmit power fault condition. figure 13 shows the shutdown logic. tables 1 and 2 show the qt thresholds as a function of i bmd current-set point. the high-bias, quick-trip alarm features an 8-bit thresh- old setting with an lsb of 8.2?. programming the hbias threshold to zero inhibits the hbias alarm flag, preventing tx-f from being asserted, the hbias alarm from causing a shutdown, and the hbias alarm bit in status from being set. the hbias enable bit can be used to prevent shutdown from occurring while allow- ing the hbias alarm flag to trigger tx-f. password protection the ds1861 has two 16-bit password entry registers (used as a 32-bit value) and two 16-bit password regis- ters (used as 32-bit value) that can be used to write-pro- tect all the configuration settings. the password entry registers, pwe high and pwe low, are the locations where the user enters the password to disable the write protection and change the device settings. the pass- word bytes, pw high and pw low, set the password to a new value. when the device is write-protected, the only bytes that can be written are the password entry bytes. to secure the password, the pw bytes always read as 0s when the pwe bytes do not match the pw bytes. once the correct password has been entered into the pwe bytes, the password can also be read from the pw registers. because the pwe bytes can be read all the time, it is recommended that the pwe bytes are written to all 1s once the desired settings are modified to prevent anyone from simply reading pwe to attain the password. the pwe bytes are sram, so they reset themselves to 1s if v cc drops below v poa . in addition to write protection, the password must also be entered and the ds1861 must be halted to read the i biasset and i modset dac codes. see the reading the biasset and modset registers section for more information about reading the dac codes. ds1861 full laser control with fault management ____________________________________________________________________ 17 htxp_thresh<2:0> high-transmit power threshold (i set ) 000 disabled* 001 do not use 010 1.30 011 1.43 100 1.56 101 1.69 110 1.82 111 1.95 table 1. htxp threshold settings * disabled inhibits the htxp qt from causing a shutdown or asserting tx-f. ltxp_thresh<2:0> low-transmit power threshold (i set ) 000 disabled* 001 do not use 010 0.81 011 0.76 100 0.54 101 0.41 110 0.28 111 0.14 table 2. ltxp threshold settings * disabled inhibits the ltxp qt from causing a shutdown or asserting tx-f.
ds1861 full laser control with fault management 18 ____________________________________________________________________ ds1861 memory map word 0 word 1 word 2 word 3 base addr row name byte 0/8 byte 1/9 byte 2/a byte 3/b byte 4/c byte 5/d byte 6/e byte 7/f 78h password entry status sram sram pwe high pwe low reserved b0h apc config user ee user ee apc user ee er (n) modload control b8h fast comp htxp threshold ltxp threshold hbias threshold user ee user ee user ee user ee user ee c0h password reserved reserved reserved pw high pw low reserved d0h dac codes reserved i biasset code reserved reserved reserved reserved i modset code expanded bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 byte addr byte name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 78h status shutdown flag htxp shutdown ltxp shutdown hbias shutdown poa htxp alarm ltxp alarm hbias alarm 7bh pwe high 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 7dh pwe low 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b2h apc gain2 gain1 gain0 2 4 2 3 2 2 2 1 2 0 b4h er (n) rsel 2 6 2 5 2 4 2 3 2 2 2 1 2 0 b5h modload 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ee ee ee ee b7h control modload enable htxp enable ltxp enable hbias enable dpol soft tx-d excite disable halt b8h high tx-p alarm threshold ee ee ee ee ee 2 2 2 1 2 0 b9h low tx-p alarm threshold ee ee ee ee ee 2 2 2 1 2 0 bah high bias alarm threshold 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 c3h pw high 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 c5h pw low 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 d1h i biasset code 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 d6h i modset code 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 0 0 0 0 key: sram eeprom note: 0 indicates an unused bit that reads as 0.
ds1861 full laser control with fault management ____________________________________________________________________ 19 detailed register description conventions name of row name of byte... < write access >< volatility >< power- up/factory default value > 0. name of bit 0.....bit 0 description 1. name of bit 1.....bit 1 description 2 to 7. bit names.....bit 2 to 7 descriptions write access: w is write-only access, r is read-only access, and r/w is read/write access. a password may be required for write access on r/w registers. see the memory map for complete access code descriptions. volatility: v is volatile (sram), nv is nonvolatile (eeprom). power-up/factory default value: for sram registers, this value is always the power-up value. for eeprom registers, this is the factory default value. these can be permanently modified by entering the password and writing the register. n/a is used for hardware-depen- dent values, such as alarm flags. password entry status 0. hbias alarm.....high bias-current alarm. this flag is high when i biasset hbias alarm threshold. this flag is updated every 4? or 16? depending on the state of the convergence algorithm. programming hbias threshold byte to zero disables the hbias alarm. 1. ltxp alarm.....low transmitted power alarm. this flag is high when the i bmd current drops below the value set by the ltxp threshold. this flag is updated every 16?. programming ltxp threshold to zero disables this flag. this flag willl be high when tx-d = 1 unless the alarm has been disabled. 2. htxp alarm....high transmitted power alarm. this flag is high when the i bmd current rises above the value set by the htxp threshold. this flag is updated every 16?. programming htxp threshold to zero disables this flag. 3. poa....analog power-on reset alarm (v cc power good). this flag is set when v cc < v poa . 4. hbias shutdown....this flag goes high when a hbias safety fault is generated and hbias enable is high. hbias shutdown goes low with poa or a falling edge of the tx-d pin, providing the safety fault is no longer present. 5. ltxp shutdown....this flag goes high when a ltxp safety fault is generated and ltxp enable is high. ltxp shutdown goes low with poa or a falling edge of tx-d, providing the safety fault is no longer present. 6. htxp shutdown....this flag goes high when a htxp safety fault is generated and htxp enable is high. htxp shutdown goes low with poa or a falling edge of tx-d, providing the safety fault is no longer present. 7. shutdown flag....this flag is high when any of the three latched safety faults are high ( hbias shutdown, ltxp shutdown, or htxp shutdown ), and it remains high after the individual flag? are reset until fault reset time has elapsed. pwe high & low .... until the cor- rect 32-bit password is written to pwe, the pwe bytes are the only locations that can be written. pwe should be written to a value other than the password once the device? configuration has been updated to prevent the password from being read from pwe. after a power cycle these locations will each be reset to ffffh. apc config apc ....<00h> sets the desired value of the feedback current into the i bmd pin. the 3 msb? determine the input gain value according to this table: the remaining 5 lsbs determine the i bmd current set- point (i set ) assuming a gain of 1. the formula for the i bmd current setpoint with the gain is then given by: i set = 1.525? gain (apc <4:0> + 32) if values greater than 10011111b (9fh) are pro- grammed into the apc register, the ds1861 will clamp i set to its maximum value, equivalent to if the register was set to 10011111b. er (n) ....<1ch> sets the gain ( n ) on the measured excitation current used to generate i modset . this sets the extinction ratio of the system. higher n values increase the excitation ratio. the msb of this register (rsel) is a flag that selects a high (rsel = 1) or low (rsel = 0) range for n . the 7 lsbs of the regis- ter determine the actual n code. the value of n can be calculated by the following equation: apc<7:5> gain 000 1 001 2 010 4 011 8 1xx 16
ds1861 full laser control with fault management 20 ____________________________________________________________________ the default setting of er = 1ch corresponds to n = 30, which is the minimum useable value. the maximum useable value is n = 136 (er = e8h). for more informa- tion refer to the automatic extinction ration control section. modload .....<0000h> this register determines the startup value of i modset following a falling edge of tx-d when modload_enable = 1 and no fault condition has occurred. this 12-bit register value is left justified in a 16-bit register. the 4 lsbs default to 0s. control .....<70h> this byte is used to enable/disnable the shutdown alarms and configure several other settings. writing to this byte causes an eeprom write cycle, even if only the halt bit (sram) is changed. it should not be modified more than the specified number of write cycles. 0. halt.....setting this bit high stops the control loop and freezes the outputs at their present state. once the control loop is stopped the i biasset and i modset output registers can be read. this bit is sram and resets to zero when v cc drops below v poaf . 1. excite_disable.....setting this bit high prevents the ds1861 from entering the excitation state (it does not add the disturbance current), which disables automatic extinction ratio control. i modset will remain at its last value until reset by a fault or set to modload. 2. soft_tx-disable.....this bit is ored with the tx-d pin to create the internal tx-disable signal. so asserting either soft_tx-disable or the tx-d pin will disable the outputs. both soft_tx-disable and tx-d must be deasserted for the outputs to operate. 3. dpol.....diode polarity. set to 0 to have the bmd pin source current. set to 1 to have bmd sink current. 4. hbias_enable.....set high to allow a safety fault caused by high bias alarm shut the part down. 5. ltxp_enable.....set high to allow a safety fault caused by low transmitted power alarm shut the part down. 6. htxp_enable.....set high to allow a safety faultl caused by high transmitted power alarm shut the part down. 7. modload_enable.....if high, i modset loads the value in modload on the falling edge of tx-d when no fault condition is present. otherwise, i modset will return to operation with its value prior to when tx-d was asserted. quick-trip monitors htxp threshold .....<00h> sets the threshold current for the htxp alarm. the alarm trips when i bmd > i bmd setpoint ?[1 + ( htxp threshold<2:0> ) 0.125]. set to 00h to disable the alarm. ltxp threshold .....<00h> sets the threshold current for the ltxp alarm. the alarm trips when i bmd < i bmd setpoint ?[1 - ( ltxp threshold<2:0> ) 0.125]. set to 00h to disable the alarm. hbias threshold .....<00h> sets the threshold current for the high bias current alarm. the alarm trips when bias current is 7.625? x ( hbias threshold) . this register value is compared directly against the i biasset code value in register d1h to determine if an alarm condition has occurred. set hbias threshold to 00h to disable this alarm. password pw high and low .....<0000h> the pwe value is compared against the value written to these locations to determine if the user has write access to password-protected memory locations. these locations read as zeros unless the password has been entered into pwe to ensure the password remains secure. dac codes i biasset code .....<00h> this is the most signicant byte of the 18-bit i biasset dac code. i biasset = 7.625? x (i biasset code). the part must be halted and the password must be entered to read this value. i modset code .....<0000h> the i modset dac code. the lsb weight of the i modset dac code is 477na. thus, i modset = 477na x (i modset code). the part must be halted and the password entered to read this value. the four least significant bytes of this register read as 0s. : : n er rsel er rsel = <>+ = <>+ = ? ? ? ? ? 60 32 2 0 60 32 1
ds1861 full laser control with fault management ____________________________________________________________________ 21 i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses, and start and stop conditions. slave devices: slave devices send and receive data at the master? request. bus idle or not busy: time between stop and start conditions when both sda and scl are inactive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. see the timing dia- gram for applicable timing. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high gener- ates a stop condition. see the timing diagram for applicable timing. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data trans- fer following the current one. repeated starts are com- monly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identically to a normal start con- dition. see the timing diagram for applicable timing. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements (figure 14). data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time (figure 14) before the next rising edge of scl during a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. remember that the master gener- ates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowledgement (ack) or not acknowledge (nack) is always the 9th bit transmitted during a byte transfer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device per- forms a nack by transmitting a one during the 9th bit. timing (figure 14) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. sda scl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop note: timing is reference to v il(max) and v ih(min) . start figure 14. i 2 c timing diagram
ds1861 full laser control with fault management 22 ____________________________________________________________________ byte write: a byte write consists of 8 bits of informa- tion transferred from the master to the slave (most sig- nificant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the mas- ter are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to ter- minated communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave addressing byte sent immediately following a start condition. the slave address byte (figure 15) contains the slave address in the most sig- nificant 7 bits and the r/ w bit in the least significant bit. the ds1861? slave address is 1010a 2 a 1 a 0 (binary), where a 2 , a 1 , and a 0 are the values of the address pins. the address pins allow the device to respond to one of eight possible slave addresses. by writing the correct slave address with r/ w = 0, the master indi- cates it will write data to the slave. if r/ w = 1, the mas- ter will read data from the slave. if an incorrect slave address is written, the ds1861 assumes the master is communicating with another i 2 c device and ignore the communications until the next start condition is sent. memory address: during an i 2 c write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte trans- mitted during a write operation following the slave address byte. i 2 c communication writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data and generate a stop condition. remember the master must read the slave? acknowledgement during all byte write operations. writing multiple bytes to a slave: to write multiple bytes to a slave the master generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address, writes up to 8 data bytes and gener- ates a stop condition. the ds1861 can write 1 to 8 bytes (referred to as 1 row) with a single write transaction. this is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. the address counter limits the write to one row of the mem- ory map. attempts to write to additional memory rows without sending a stop condition between rows will result in the address counter wrapping around to the beginning address of the present row. example: a 3-byte write starts at address beh and writes three data bytes (11h, 22h, and 33h) to three ?onsecu- tive?addresses. the result would be addresses beh and bfh would contain 11h and 22h, respectively, and the third data byte, 33h, would be written to address b8h. to prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the row, and then wait for the bus free or eeprom write time to elapse. then the master can generate a new start con- dition, write the slave address byte (r/ w = 0), and the first memory address of the next memory row before continuing to write data. acknowledge polling: any time eeprom is written, the ds1861 requires the eeprom write time (t w ) after the stop condition to write the contents of the row to eeprom. during the eeprom write time, the ds1861 does not acknowledge its slave address because it is busy. it is possible to take advantage of this phenome- non by repeatedly addressing the ds1861, which allows the next row to be written as soon as the ds1861 is ready to receive the data. the alternative to acknowl- edge polling is to wait for maximum period of t w to elapse before attempting to write again to the ds1861. eeprom write cycles: when eeprom writes occur, the ds1861 will write the whole eeprom memory row even if only a single byte on the row was modified. writes that do not modify all 8 bytes on the row are allowed and do not corrupt the remaining bytes of memory on the same row. because the whole row is written, bytes on the row that were not modified during the transaction are still subject to a write cycle. this 7-bit slave address most significant bit a 2 , a 1 and a 0 pin values determines read or write r/w 1 01 0 a 2 a 1 a 0 figure 15. slave address byte
can result in a whole row being worn out over time by writing a single byte repeatedly. writing a row one byte at a time will wear out the eeprom eight times faster than writing the entire row at once. the ds1861? eeprom write cycles are specified in the nonvolatile memory characteristics table. reading a single byte from a slave: unlike the write operation that uses the memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave at the location currently in the address counter; the master generates a start condition, writes the slave address byte with r/ w = 1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this the master gen- erates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. figure 16 shows a read example using the repeated start condition to specify the starting memory location. reading multiple bytes from a slave: the read oper- ation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the mas- ter reads the last byte, it nacks to indicate the end of the transfer and generates a stop condition. this can be done with or without modifying the address counter? location before the read cycle. ds1861 full laser control with fault management ____________________________________________________________________ 23 xxxxxxxx 101 0 a 0 0 a 1 a 2 101 0 a 0 0 a 1 a 2 101 0 a 0 0 a 1 a 2 101 0 a 0 0 a 1 a 2 101 0 a 0 0 a 1 a 2 101 0 a 0 0 a 1 a 2 communications key write a single byte write up to an 8-byte page with a single transaction read a single byte with a dummy write cycle to set the address counter read multiple bytes with a dummy write cycle to set the address counter 8-bits address or data white boxes indicated the master is controlling sda notes 2) the first byte sent after a start condition is always the slave address followed by the read/write bit. shaded boxes indicated the slave is controlling sda start ack not ack s s s s s a a a a a a a p a asr sr a a a p n p n p a a d ata d ata d ata d ata d ata d ata d ata memory address memory address memory address memory address d ata aa a pn sr stop repeated start 1) all bytes are sent most significant bit first. figure 16. i 2 c communications examples
ds1861 applications information calibrating apc and extinction ratio before calibrating, the apc register should be set to a low value to ensure the laser? maximum power level is not exceeded before the power level is calibrated. additionally, the er register should be set to its mini- mum value (28 decimal) to ensure that a data test pat- tern does not cause the laser to shut off. once the apc and er registers are at minimal values, enable a data pattern and calibrate the average power level first. calibrating the average power level while sending data through the laser diode, increase the value in the apc register until the light output matches the desired average power level. the average power level is the arithmetic average of the 1 and 0 power levels. calibrating the extinction ratio while sending data through the laser diode, begin increasing the er register from its minimum value of 28 decimal (1ch), until the proper extinction ratio is reached or the maximum setting (104 decimal or 68h) of the low range is reached. if the maximum low range value is reached, write the er register to 156 decimal (9ch), which switches the extinction ratio value to the minimum value of the high range. continue increasing the er setting until the proper extinction ratio is reached. if the maximum value of the high range set- ting is reached (232 decimal or e8h) without reaching the proper extinction ratio, then either the desired extinction ratio cannot be reached or a problem is pre- venting the system from operating properly. addressing multiple ds1861s on a common i 2 c bus up to eight ds1861s can be addressed on a single i 2 c bus by using the device? address inputs (a 2 , a 1 , a 0 ) to change its slave address. for information about device addressing, see the i 2 c communications s ection. power-supply decoupling to achieve best results, it is recommended that the power supply is decoupled with a 0.01? or a 0.1? capacitor. use high-quality, ceramic, surface-mount capacitors, and mount the capacitors as close as possible to the v cc and gnd pins to minimize lead inductance. bmd shunt capacitor the bmd shunt capacitor works with the internal resis- tance of the bmd input to provide a lowpass filter that reduces the effects of noise on the apc loop. its capacitance value must be chosen carefully to ensure that it is both large enough to provide good filtering of high-frequency noise and small enough that it does not cause the control loop to become unstable. a 1nf, 10% tolerant, x7r ceramic capacitor is recommended. sda and scl pullup resistors sda is an open-collector bidirectional data pin on the ds1861 that requires a pullup resistor to realize high logic levels. either an open-collector output with a pullup resistor or a push-pull output driver can be used for the scl input. pullup resistor values should be cho- sen to ensure that the rise and fall times listed in the ac electrical characteristics table are within specification. full laser control with fault management 24 ____________________________________________________________________
ds1861 full laser control with fault management maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . chip information transistor count: 55,677 substrate connected to ground 14 13 12 11 10 9 8 1 2 3 4 5 6 7 v cc modset a 2 a 1 tx-d tx-f scl sda top view a 0 biasset n.c. gnd bmd n.c. ds1861 pin configuration
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1861 part number table notes: see the ds1861 quickview data sheet for further information on this product family or download the ds1861 full data sheet (pdf, 712kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis DS1861B+ csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16+1 * 0c to +70c rohs/lead-free: yes materials analysis DS1861B csbga;16 pin;157 dwg: 56-g6005-001b (pdf) use pkgcode/variation: x16-1 * 0c to +70c rohs/lead-free: no materials analysis ds1861e+ tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14+3 * 0c to +70c rohs/lead-free: yes materials analysis
ds1861e tssop;14 pin;173 dwg: 56-g2015-000b (pdf) use pkgcode/variation: u14-3 * 0c to +70c rohs/lead-free: no materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy

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